The semiconductor industry has continually sought ways to produce memory devices with an increased number of memory cells per memory die. In non-volatile memory (e.g., NAND flash memory), one way to increase memory density is by using a vertical memory array, which is also referred to as a three-dimensional (3-D) memory array. One type of vertical memory array includes semiconductor pillars that extend through openings (e.g., holes) in layers of conductive material (also referred to as word line plates or control gate plates), with dielectric materials at each junction of the semiconductor pillars and the conductive materials. Thus, multiple transistors can be formed along each pillar. Vertical memory array structures enable a greater number of transistors to be located in a unit of die area by building the array upwards (e.g., vertically) on a die, as compared to structures with traditional planar (e.g., two-dimensional) arrangements of transistors.
Vertical memory arrays and methods of forming them are described in, for example: U.S. Patent Application Publication No. 2007/0252201 of Kito et al., now U.S. Pat. No. 7,936,004, issued May 3, 2011; Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15 (2007); Fukuzumi et al., “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory,” IEDM Technical Digest, pp. 449-52 (2007); and Endoh et al., “Novel Ultrahigh-Density Flash Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEEE Transactions on Electron Devices, vol. 50, no. 4, pp. 945-951 (April, 2003).
Conventional vertical memory arrays require an electrical connection between the conductive materials (e.g., word line plates or control gates) and access lines (e.g., word lines) so that memory cells in the 3-D array may be uniquely selected for writing or reading functions. One method of forming an electrical connection includes forming a so-called “stair-step” structure at the edge of the conductive materials. FIGS. 1A through 1D show one conventional method of creating a stair-step structure 10 in a stack of conductive materials 12. As shown in FIG. 1A, conductive materials 12 are separated by insulating materials 14 between the conductive materials 12. A mask 16 (e.g., photoresist material) is formed over the topmost insulating material 14 and patterned to expose a portion of the insulating material 14a, the exposed portion having a width of one so-called “step” of the stair-step structure 10 to be formed. An anisotropic etch 18, such as a reactive ion etch (RIE) or other dry etch, is performed to remove the insulating material 14a at the portion exposed through the mask 16. The pattern in the insulating material 14a is then transferred to the conductive material 12a. The exposed insulating material 14a is removed by one dry etch process that stops on the conductive material 12a, and the exposed conductive material 12a is then removed by another dry etch process that stops on the insulating material 14b. Next, the mask 16 is reduced in size by removing a portion of the mask (also known as “trimming”), such as by isotropic etching, to expose another portion of the insulating material 14a, as shown in FIG. 1B.
The process is repeated by subjecting the structure to an anisotropic etch 18, including removing exposed portions of the two insulating materials 14a and 14b and subsequently removing exposed portions of the two conductive materials 12a and 12b. As shown in FIG. 1C, the successive reduction in size of the mask 16 and the repeated dry etch processes are continued until the insulating material 14c and conductive material 12c is exposed, the mask 16 is removed, and a stair-step structure 10 remains. Word line contacts 20 are formed to extend through each respective insulating material 14 and electrically contact each conductive material 12, as shown in FIG. 1D. The top of each word line contact 20, as viewed in FIG. 1D, connects to a conductive word line (not shown). While FIGS. 1A through 1D illustrate using two anisotropic etches 18 to create three so-called “steps” of the stair-step structure 10, the acts of etching the insulating material 14, etching the conductive material 12, and trimming the mask 16 may be repeated to create more steps (and thus contact regions for word line contacts). Current conventional methods have been used to form more than eight contact regions (e.g., steps).
As the desired number of steps in the conventional stair-step structure increases, the margin of error associated with each act in the process of forming the steps correspondingly decreases when using the conventional method. For example, and as explained above, each iteration of the conventional method includes trimming the mask, etching the insulating material, and etching the conductive material. The desired number of steps is formed by repeating these acts as many times as the number of conductive materials in the stack. Each act of the conventional method has an associated etch control error because the size of each step is designed to fall within a particular range (e.g., tolerance) to allow enough room for a contact to be formed thereon while keeping the overall size of the stair-step structure small. Additionally, the relative locations of the steps are designed to fall within a range of locations in order to accurately form contacts thereon. As the number of iterations increases, any deviation from a target step width or location may be compounded because errors in one material are transferred to an underlying material. For a high number of steps in the stair-step structure, the margin of error to be achieved for the etch rate control may be less than one percent (1%). Small margins of error are difficult and costly to attain using conventional methods. Furthermore, because the mask is repeatedly trimmed, the method may start with a mask of high thickness, which may be difficult to repeatedly pattern and trim with the precision needed to have the necessary control over step width. Furthermore, the large amount of mask material is expensive and time-consuming to both faun and remove.
Space savings in a memory device incorporating a vertical memory array may be accomplished by reducing the area that a stair-step structure covers. One method of reducing this area is described in U.S. Patent Application Publication No. 2009/0310415 to Jin et al., now U.S. Pat. No. 8,325,527, issued Dec. 4, 2012. Although some space is saved by aligning the word line contacts in the same direction as the bit lines, further improvements and reductions in cost in the manufacturing of such structures, as well as alternative methods of reducing the area covered by the stair-step structures, are desired. For example, the method described in Jin et al. uses a unique mask for each etch act to form the steps, which adds significant cost because of a high number of photolithographic reticles used to form the masks. Reductions in cost and improvements in controllability of manufacturing stair-step structures are, therefore, desired.